As is known, it is desirable to be able to test and "screen" DMOS power transistors in the inspection phase by applying a stress to the gate oxide of the transistors for the purpose of reducing their failures during their operational life, by eliminating the weakest components in the inspection phase.
Furthermore, to perform validity tests in integrated power circuits, it is known to equip such circuits with dedicated contact pads to which stress voltages suitable for testing power components are applied; this technique cannot, however, be: used directly for DMOS transistors in that the high voltages that are necessary to stress the gate oxide of such components sufficiently (30 V for example) are not compatible with the control circuitry and could lead to breakage.
On the other hand, in some applications such as the motor vehicle field, it is desired to guarantee failures of operating devices tending towards 0 p.p.m. and it thus becomes increasingly necessary to have methods of test for DMOS power transistors.